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| FIN1104 LVDS 4 Port High Speed Repeater January 2002 Revised February 2002 FIN1104 LVDS 4 Port High Speed Repeater General Description This 4 port repeater is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The FIN1104 accepts and outputs LVDS levels with a typical differential output swing of 330 mV which provides low EMI at ultra low power dissipation even at high frequencies. The FIN1104 provides a VBB reference for AC coupling on the inputs. In addition the FIN1104 can directly accept LVPECL, HSTL, and SSTL-2 for translation to LVDS. Features s Greater than 800 Mbps data rate s 3.3V power supply operation s 3.5 ps maximum random jitter and 135 ps maximum deterministic jitter s Wide rail-to-rail common mode range s LVDS receiver inputs accept LVPECL, HSTL, and SSTL-2 directly s Ultra low power consumption s 20 ps typical channel-to-channel skew s Power off protection s > 7.5 kV HBM ESD Protection s Meets or exceeds the TIA/EIA-644-A LVDS standard s Available in space saving 24-Lead TSSOP package s Open circuit fail safe protection s VBB reference output Ordering Code: Order Number FIN1104MTC Package Number MTC24 Package Description 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code. Pin Descriptions Pin Name RIN1+, RIN2+, RIN3+, RIN4+ RIN1-, RIN2-, RIN3-, RIN4- Description Non-inverting LVDS Input Inverting LVDS Input Connection Diagram DOUT1+, DOUT2+, Non-inverting Driver Output DOUT3+, DOUT4+ DOUT1-, DOUT2-, Inverting Driver Output DOUT3-, DOUT4- EN EN VCC GND VBB Driver Enable Pin for All Output Inverting Driver Enable Pin or DOUT2, DOUT2, DOUT3, and DOUT4 Power Supply Ground Reference Voltage Output (c) 2002 Fairchild Semiconductor Corporation DS500656 www.fairchildsemi.com FIN1104 Function Table Inputs EN H H H X L EN L L L H X DIN+ H L X X DIN- L H X X Outputs DOUT+ H L H Z Z DOUT- L H L Z Z Functional Diagram Fail Safe Case H = HIGH Logic Level L = LOW Logic Level X = Don't Care Z = High Impedance www.fairchildsemi.com 2 FIN1104 Absolute Maximum Ratings(Note 1) Supply Voltage (VCC) LVDS DC Input Voltage (VIN) LVDS DC Output Voltage (VOUT) Driver Short Circuit Current (IOSD) Storage Temperature Range (TSTG) Max Junction Temperature (TJ) Lead Temperature (TL) (Soldering, 10 seconds) ESD (Human Body Model) ESD (Machine Model) 260C 7500V 400V -0.5V to +4.6V -0.5V to +4.6V -0.5V to +4.6V Continuous 10 mA Recommended Operating Conditions Supply Voltage (VCC) Magnitude of Differential Voltage (|VID|) Common Mode Voltage Range (VIC) Operating Temperature (TA) (0V + |VID |/2) to (VCC - |VID|/2) 100 mV to VCC 3.0V to 3.6V -65C to +150C 150C -40C to +85C Note 1: The "Absolute Maximum Ratings": are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature and output/input loading variables. Fairchild does not recommend operation of circuits outside databook specification. DC Electrical Characteristics Symbol VTH VTL VIH VIL VOD VOD VOS VOS IOS Parameter Differential Input Threshold HIGH Differential Input Threshold LOW Input HIGH Voltage (EN or EN) Input LOW Voltage (EN or EN) Output Differential Voltage VOD Magnitude Change from Differential LOW-to-HIGH Offset Voltage Offset Magnitude Change from Differential LOW-to-HIGH Short Circuit Output Current DOUT+ = 0V and DOUT- = 0V, Driver Enabled VOD = 0V, Driver Enabled IIN IOFF ICCZ ICC IOZ VIC CIN COUT VBB Input Current (EN, EN, DINx+, DINx-) VIN = 0V to VCC, Other Input = VCC or 0V (for Differential Inputs) Power Off Input or Output Current Disabled Power Supply Current Power Supply Current Disabled Output Leakage Current Common Mode Voltage Range Input Capacitance Output Capacitance Output Reference Voltage VCC = 3.3V, IBB = 0 to -275 A 1.125 VCC = 0V, VIN or VOUT = 0V to 3.6V Drivers Disabled Drivers Enabled, Any Valid Input Condition Driver Disabled, DOUT+ = 0V to 3.6V or DOUT- = 0V to3.6V |VID| = 100 mV to VCC Enable Input LVDS Input 0V + |VID|/2 2.6 2.1 2.8 1.2 1.375 5.4 30.4 -3.4 3.4 RL = 100 , Driver Enabled, See Figure 2 1.125 1.23 Test Conditions See Figure 1; VIC = +0.05V, +1.2V, or VCC - 0.05V See Figure 1; VIC = +0.05V, +1.2V, or VCC - 0.05V -100 2.0 GND 250 330 VCC 0.8 450 25 1.375 25 -6 6 20 20 11 41 20 VCC - (|VID|/2) Min Typ (Note 2) 100 Max Units mV mV V V mV mV V mV mA mA A A mA mA A V pF pF V Note 2: All typical values are at TA = 25C and with VCC = 3.3V. 3 www.fairchildsemi.com FIN1104 AC Electrical Characteristics Over supply voltage and operating temperature ranges, unless otherwise specified Symbol tPLHD tPHLD tTLHD tTHLD tSK(P) tSK(LH), tSK(HL) tSK(PP) fMAX tPZHD tPZLD tPHZD tPLZD tDJ tRJ Parameter Differential Output Propagation Delay LOW-to-HIGH Differential Output Propagation Delay HIGH-to-LOW Differential Output Fall Time (80% to 20%) Pulse Skew |tPLH - tPHL| Channel-to-Channel Skew (Note 4) Part-to-Part Skew (Note 5) Maximum Frequency (Note 6)(Note 7) Differential Output Enable Time from Z to HIGH Differential Output Enable Time from Z to LOW Differential Output Disable Time from HIGH to Z Differential Output Disable Time from LOW to Z LVDS Data Jitter, Deterministic LVDS Clock Jitter, Random (RMS) VID = 300 mV, PRBS = 223 - 1, VIC = 1.2V at 800 Mbps VID = 300 mV, VIC = 1.2V at 400 MHz RL = 100 , CL = 5 pF, See Figure 2 and Figure 3 400 800 2.2 2.5 1.8 2.1 85 2.1 5 5 5 5 135 3.5 RL = 100 , CL = 5 pF, VIC = |V ID|/2 to VCC - (|VID|/2), Duty Cycle = 50%, See Figure 1 and Figure 3 Differential Output Rise Time (20% to 80%) VID = 200 mV to 450 mV, Test Conditions Min Typ (Note 3) 0.75 0.75 0.29 0.29 1.1 1.1 0.4 0.4 0.02 0.02 0.02 1.75 1.75 0.58 0.58 0.2 0.15 0.5 Max Units ns ns ns ns ns ns ns MHz ns ns ns ns ps ps Note 3: All typical values are at TA = 25C and with VCC = 3.3V. Note 4: tSK(LH), tSK(HL) is the skew between specified outputs of a single device when the outputs have identical loads and are switching in the same direction. Note 5: tSK(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices switching in the same direction (either Low-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test circuits. Note 6: Passing criteria for maximum frequency is the output VOD > 200 mV and the duty cycle is 45% to 55% with all channels switching. Note 7: Output loading is transmission line environment only; CL is < 1 pF of stray test fixture capacitance. FIGURE 1. Differential Receiver Voltage Definitions and Propagation and Transition Time Test Circuit Note A: All LVDS input pulses have frequency = 10 MHz, t R or tF < = 0.5 ns Note B: CL includes all probe and test fixture capacitances FIGURE 3. Differential Driver Propagation Delay and Transition Time Test Circuit FIGURE 2. Differential Driver DC Test Circuit www.fairchildsemi.com 4 FIN1104 FIGURE 4. AC Waveform Note A: All LVTTL input pulses have frequency = 10MHz, tR or tF < = 2 ns Note B: CL includes all probe and jig capacitances FIGURE 5. Differential Driver Enable and Disable Circuit FIGURE 6. Enable and Disable AC Waveforms 5 www.fairchildsemi.com FIN1104 LVDS 4 Port High Speed Repeater 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC24 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com |
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